As the dimensions of semiconductor device features continue to shrink into the deep sub-micron range, as in the decananometer range, it becomes increasingly more difficult to form the features with high dimensional accuracy. The minimum size of a feature depends upon the chemical and optical limits of a particular lithography system, and the tolerance for distortions of the shape, such as corner rounding when forming negative features in a target layer or substrate.
Accordingly, a need exists for methodology enabling the fabrication of semiconductor devices having accurately formed features in the deep sub-micron range, such as features of 45 nm and under, in addition to features used for 65 nm technology and beyond, e.g., less than 90 nm half pitch, line end shortening, line-to-line printing and T-shape printing. There exists a particular need for such enabling methodology that can be performed efficiently, at low manufacturing cost, and in a single tool for high manufacturing throughput.